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YTD427 application manual iafe isdn dsu analog front end YTD427 application manual catalog no. : lsi-6td427a2 1997.12
b impor t ant notice 1. y amaha reserv es the righ t to mak ec hanges to its pro ducts and to this do cumen t with- out notice. the information con tained in this do cumen t has b een carefully c hec k ed and is b eliev ed to be reliable. ho w ev er, y amaha assumes no resp onsibilities for inaccura- cies and mak es no commitmen t to up date or to k eep curren t the information con tained in this do cumen t. 2. these y amaha pro ducts are designed only for commercial and normal industrial ap- plications, and are not suitable for other uses, suc h as medical life supp ort equipmen t, n uclear facilities, critical care equipmen tor an y other application the failure of whic h could lead to death, p ersonal injury or en vironmen tal or prop ert y damage. use of the pro ducts in an y suc h application is at the customer's sole risk and exp ense. 3. y amaha assumes no liabilit y for inciden tal, consequen tial or sp ecial damages or injury that ma y result from misapplication or improp er use or op eration of the pro ducts. 4. y amaha mak es no w arran t y or represen tation that the pro ducts are sub ject to in- tellectual prop ert y license from y amaha or an y third part y , and y amaha mak es no w arran t y or represen tation of non-infringemen t with resp ect to the pro ducts. y amaha sp ecically excludes an y liabilit y to the customer or an y third part y arising from or related to the pro ducts' infringemen tof an y third part y's in tellectual prop ert y righ ts, including the paten t, cop yrigh t, trademark or trade secret righ ts of an y third part y . 5. examples of use describ ed herein are merely to indicate the c haracteristics and p er- formance of y amaha pro ducts. y amaha assumes no resp onsibilit y for an y in tellectual prop ert y claims or other problems that ma y result from applications based on the ex- amples describ ed herein. y amaha mak es no w arran t y with resp ect to the pro ducts, express or implied, including, but not limited to the w arran ties of merc han tabilit y , tness for a particular use and title.
con ten ts 1 intr oduction 3 1.1 general description : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 3 1.2 f eatures : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 3 2 block dia gram 5 3 pin descriptions 7 3.1 pin assignmen ts : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 3.2 pin f unctions : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8 4 functions 11 5 electrical chara cteristics 13 5.1 absolute maxim um ratings : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 13 5.2 recommended op erating conditions : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 14 5.3 dc characteristics : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 15 5.4 a c characteristics : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 17 6 p a cka ge outline 19 appendix a exmaple of applica tions 21 a.1 example of application circuits : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 21 1
2 contents
chapter 1 intr oduction 1.1 general description YTD427 is a comm unication lsi whic h pro vides the isdn subscrib er in terface (t w o-wire metallic time com- pression m ultiplexing op eration). it is capable of pro viding the electric c haracteristics conforming to ttc standard jt-g961. a dsu (digital service unit) can easily b e constructed b y com bining with ytd426b. 1.2 f eatures 1. automatic gain con trol (a gc) function 2. filter function 3. p eak hold function 4. adc (analog digital con v erter) function 5. lo wp o w er consumption op eration mo de 72mw(t yp.) 6. cmos tec hnology 7. 64-pin qfp 8. single +5 v olt supply 3
4 chapter 1. intr oduction
chapter 2 block dia gram ytd 427 in ternal blo c k diagram is sho wn in figure2.1. agc filter peak holder adc digital (receive data) ytd426b u reference point interface i/f figure 2.1: in ternal blo c k diagram 5
6 chapter 2. block dia gram
chapter 3 pin descriptions 3.1 pin assignmen ts the pin assignmen ts of YTD427 are sho wn in figure 3.1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 sgbp sxa sxb nc2 nc3 a1 a0 test6 rwn strbn d15 d3 d4 d10 d11 d13 d14 d8 d6 39 40 41 42 43 44 45 46 47 48 vrb 38 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 atei ateo test5 d12 d5 d9 d7 adck test4 test2 test1 fthn vrbs vrt sgr sga rxs sgb d0 d1 d2 test0 rstn nc4 nc1 test3 vrts rxu dv ss av ss dv dd dv dd dv ss dv ss dv dd dv dd dv ss av ss av dd av dd av dd av dd av ss av ss figure 3.1: YTD427-f (64-pin qfp) pin assignmen ts [t op view] 7
8 chapter 3. pin descriptions 3.2 pin f unctions pin no. pin name i/o f unction remarks 1 sgb connect a 0.015 f capacitor across the sgb and sgr pins. 2 sgbp connect a 0.015 f capacitor across the sgbp and sgr pins. 3 sxa connected to sxb. 4 sxb connected to sxa. 5, 48, 58, 59 a v ss gnd analog ground all pins m ust be joined together. 6, 26, 27, 47 d v ss gnd digital ground all pins m ust be joined together. 7 nc1 in un used connected to d v ss 8 nc2 in un used connected to d v ss 9 nc3 in un used connected to d v ss 10 test5 in t est input 5 connected to d v ss 11 a1 in address bus bit 1 connected to addres1 of ytd426b 12 a0 in address bus bit 0 connected to addres0 of ytd426b 13 test6 in t est input 6 connected to d v ss 14 r wn in read/write signal \h" : read \l" : w rite connected to r wn of ytd426b 15 strbn in strob e signal \h" : inactiv e \l" : activ e connected to strbn of ytd426b 16, 17, 36, 37 d v dd pwr digital p o w er supply all pins m ust be joined together.
3.2. pin functions 9 pin no. pin name i/o f unction remarks 18 d15 out data bus bit 15 connected to afed a t a15 of ytd426b. 19 d14 out data bus bit 14 connected to afed a t a14 of ytd426b. 20 d13 out data bus bit 13 connected to afed a t a13 of ytd426b. 21 d12 out data bus bit 12 connected to afed a t a12 of ytd426b. 22 d11 out data bus bit 11 connected to afed a t a11 of ytd426b. 23 d10 out data bus bit 10 connected to afed a t a10 of ytd426b. 24 d9 out data bus bit 9 connected to afed a t a9 of ytd426b. 25 d8 out data bus bit 8 connected to afed a t a8 of ytd426b. 28 d7 in data bus bit 7 connected to afed a t a7 of ytd426b. 29 d6 in data bus bit 6 connected to afed a t a6 of ytd426b. 30 d5 in data bus bit 5 connected to afed a t a5 of ytd426b. 31 d4 in data bus bit 4 connected to afed a t a4 of ytd426b. 32 d3 in data bus bit 3 connected to afed a t a3 of ytd426b. 33 d2 in data bus bit 2 connected to afed a t a2 of ytd426b. 34 d1 in data bus bit 1 connected to afed a t a1 of ytd426b. 35 d0 in data bus bit 0 connected to afed a t a0 of ytd426b.
10 chapter 3. pin descriptions pin no. pin name i/o f unction remarks 38 adck in adc op eration clo c k signal connected to clk640k of ytd426b. 39 test4 in t est input 4 connected to d v ss . 40 test3n i/o t est input 3 usually xed to "h". 41 test2 in t est input 2 connected to d v ss . 42 test1 in t est input 1 connected to d v ss . 43 test0 in t est input 0 connected to d v ss . 44 rstn in reset input pin \l" : reset reset time is 2 s(minim um) 45 fthn in t est input usually xed to "h". 46 nc4 in un used connected to d v ss . 49 vrbs out adc reference p o w er supply output (lo wv oltage) 50 vrb in adc reference p o w er supply input (lo wv oltage) 51 vr t in adc reference p o w er supply input (high v oltage) 52 vr ts out adc reference p o w er supply output (high v oltage) 53, 54, 62, 63 a v dd pwr analog p o w er supply all pins m ust be joined together. 55 a tei in t est signal input connected to a v ss . 56 a teo i/o t est signal input, output connected to a v ss . 57 sgr out analog signal reference output 60 rxu in receiv e signal input 61 sga connect a 0.0047 f capacitor across sga and sgr. 64 rxs connect a 0.0022 f capacitor across rxs and sgr.
chapter 4 functions receiv ein terface receiv e pin rxu has a high input imp edance. an example of a reference circuit of the receiv ein terface is sho wn in figure 4.1. rxu sgr r=1.2k (1%) r=3.9k (1%) YTD427 figure 4.1: receiv ein terface connection a gc the a gc section adjusts the gain in 0.22 db step in the range from 0.0 to 56.1 db at the receiv e signal cen ter frequency (f=160 khz) and amplies the receiv e signal amplitude to the maxim um dynamic range. filter the lter section is to prev en t the adc and the p eak hold section from erro- neous op eration caused b y high-frequency noise. p eak hold section p eak hold is p erformed during the initial training so that the gain of the a gc section is set to mak e b est comm unication condition. adc the adc section mak es an a/d con v ersion of the receiv ed signal and trans- fers it to ytd426b. the a/d con v ersion timing is sync hronized to the clo c k (adck) pro vided b y ytd426b. digital in terface the digital section pro vides the in terface to ytd426b. 11
12 chapter 4. functions
chapter 5 electrical chara cteristics 5.1 absolute maxim um ratings (d v ss =a v ss =0.0v t a =25 ? ) p arameters sym bol min. max. units supply v oltage (digital) d v dd 0 : 3 +7.0 v supply v oltage (analog) a v dd 0 : 3 +7.0 v input v oltage (digital) d v in d v ss 0 : 3 d v dd +0.3 v input v oltage (analog) a v in a v ss 0 : 3 a v dd +0.3 v output v oltage (digital) d v out d v ss 0 : 3 d v dd +0.3 v output v oltage (analog) a v out a v ss 0 : 3 a v dd +0.3 v p o w er dissipation p d 400 mw op erating t emp erature t op 20 +70 ? storage t emp erature t st 55 +125 ? note 1 the v alues represen t the minim um and maxim um v oltages that can b e applied to the pins without causing damage. it do es not guaran tee the op eration. applying a v oltage exceeding the absolute maxim um ratings ma y cause p ermanen t damage to YTD427. note 2 use digital po w er supply d v dd and analog po w er supply a v dd under the condition: d v dd = a v dd . also, insert a c 0.1 f across d v dd and d v ss and across a v dd and a v ss to prev en t latc h up. note 3 use digital ground d v ss and analog ground a v ss under the condition: d v ss =a v ss . note 4 ev en though digital p o w er supply d v dd and analog p o w er supply a v dd ha v e the same pin name, they are not connected inside YTD427. mak e sure to connect the pins that ha v e the same name. note 5 ev en though digital ground d v ss and analog ground a v ss ha v e the same pin name, they are not connected inside YTD427. mak e sure to connect the pins that ha v e the same name. 13
14 chapter 5. electrical chara cteristics 5.2 recommended op erating conditions (d v ss =a v ss =0.0v z t a =25 ? ) p arameters sym bol condition min. t yp. max. units digital p o w er supply v oltage d v dd 4.75 5.0 5.25 v analog p o w er supply v oltage a v dd 4.75 5.0 5.25 v digital input v oltage d v in d v ss d v dd v analog input v oltage a v in a v ss a v dd v digital output v oltage d v in d v ss d v dd v analog output v oltage a v in a v ss a v dd v op erating t emp erature range t op 20 25 70 ? external clo c k input clo c kf requency f cp (note1) 0.64 mhz clo c kf requency allo w able deviation f cp (note1) 50 50 ppm clo c k dut y t duty (note1) 45 50 55 % high lev el time t w ch (note1) 400 ns lo w lev el time t w cl (note1) 400 ns rise time t tlhc (note1) 20 ns f all time t thlc (note1) 20 ns ytd426 supply input signal high-lev el pulse width t wdh (note2) 90 ns lo w-lev el pulse width t wdl (note2) 90 ns rise time t tlhd (note2) 10 ns f all time t thld (note2) 10 ns note 1 with resp ect to adck pin. note 2 with resp ect to a1, a0, r wn, strbn, d15 to d0 pins.
5.3. dc chara cteristics 15 5.3 dc characteristics (d v dd =a v dd =4.75 ? 5.25v, d v ss =a v ss =0.0v, t a =25 ? ) p arameters sym bol condition min. t yp. max. units high-lev el input v ihc (note1) 0.7d v dd d v dd v v oltage (cmos) lo w-lev el input v ilc (note1) 0.0 0.3d v dd v v oltage (cmos) input leak i lic (note1) 10 a curren t (cmos) (note2) high-lev el v iht (note3) 2.0 d v dd v input v oltage (ttl) lo w-lev el input v il t (note3) 0.0 0.8 v v oltage (ttl) input leak i lit (note3) 10 a curren t (ttl) (note4) high-lev el output v oht (note3) 4.4 v v oltage (ttl) (note5) lo w-lev el output v ol t (note3) 0.4 v v oltage (ttl) (note6) supply curren t i dd1 (note7) 14.4 24.9 ma (normal) supply curren t i dd4 (note7) 4.4 7.6 ma (at reset) (note8) p o w er consumption p tot1 (note7) 72 131 mw (normal) p o w er consumption p tot4 (note7) 22 40 mw (at reset) (note8) note1 with resp ect to adck, test4, test2 to test0, rstn, fthn, nc4 to nc1 pins. note2 v ic =d v ss -d v dd note3 with resp ect to a1, a0, r wn, strbn, d15 to d0, test3, test5, test6 pins. note4 v it =d v ss -d v dd note5 i oh = 4ma note6 i ol =12ma note7 neither external circuit nor parts note8 adck pin xed to d v ss
16 chapter 5. electrical chara cteristics (d v dd =a v dd =4.75 ? 5.25v, d v ss =a v ss =0.0v, t a =25 ? ) p arameters sym bol condition min. t yp. max. units analog output allo w able z o (note1) 30 k
load imp edance analog receiv e buer z i1 (note2) 10 m
input imp edance analog receiv e buer z i2 (note3) 100 k
input imp edance reference resistance r ref (note4) 1.92 2.40 3.84 k
v oltage divider r div (note5) 1.44 1.80 2.88 k
resistance analog signal reference v sg (note6) 0.5a v dd -0.05 0.5a v dd 0.5a v dd +0.05 v v oltage adc high-lev el reference v r t (note7) 0.7a v dd a v dd v v oltage lev el lo w-lev el reference v rb (note8) 0.0 0.3a v dd v v oltage lev el self-bias vr t v r ts (note9) 0.7a v dd -0.1 0.7a v dd 0.7a v dd +0.1 v self-bias vrb v rbs (note10) 0.3a v dd -0.1 0.3a v dd 0.3a v dd +0.1 v note1 with resp ect to sgr, sxa pins. note2 with resp ect to rxu pin. note3 with resp ect to sxb pin. note4 across vr t and vrb pins. vrb=1.5 v note5 across vr t and a v dd pins and across vrb and a v ss pins. note6 sgr pin is op en. note7 with resp ect to vr t pin. note8 with resp ect to vrb pin. note9 short vr t pin and vr ts pin note10 short vrb pin and vrbs pin
5.4. a c chara cteristics 17 5.4 a c characteristics (d v dd =a v dd =4.75 ? 5.25v, d v ss =a v ss =0.0v, t a =25 ? ) p arameters sym bol condition min. t yp. max. units t otal harmonic distortion thd 1.0 % gain g a 43.76 45.76 47.76 db a gc noise n oag 6 mv rms dc oset v oltage v ago 50 mv filter cut o f requency f c 213 320 427 khz flatness a p 1 : 0 0.0 1.0 db max. con v ersion time f ph 160 200 khz ph refresh time t phr 60 100 ns p eak hold error v phe 50 mv resolution r es 8 bit linearit y error el 1.0 2.0 lsb adc quan tization error e e 1 : 0 1.0 lsb max. con v ersion time f ad 1.28 msps clo c kf requency f adck 640 khz
18 chapter 5. electrical chara cteristics
chapter 6 p a cka ge outline 1 16 17 32 33 48 49 64 14.00 ? 0.20 18.70 ? 0.40 14.00 ? 0.20 18.70 ? 0.40 0.10 ? 0.10 (stand off) 2.20 ? 0.20 2.60 max. (installation height) p-0.80 typ. 0.35 ? 0.10 (2.35 ? 0.20) (1.50 ? 0.20) 0-10 ? lead thickness : 0.15 +0.10 -0.05 (unit) : mm (millimeters) the shape of the molded corner may be slightly different from the shape in this diagram. the figure in the parenthesis ( ) should be used as a reference. plastic body dimensions do not include burr of resin. note : the lsis for surface moun t need sp ecial consideration on storage and soldering conditions. f or detailed information, please con tact y our nearest y amaha agen t. 19
20 chapter 6. p a cka ge outline
app endix a exmaple of applica tions a.1 example of application circuits an example of an application circuit using YTD427 is sho wn in figure a.1. a0,a1 d0 ? d15 rwn strbn adck nc1 ? 4 addres0,1 afedata0 ? 15 rwn strbn clk64 a 0.1u sga rxs sgb sgbp sxa sxb 0.0047u(10%) 0.0022u(10%) 0.015u(10%) 0.15u(10%) test0,1,2,4,5,6 atei ateo a 0.1u vrbs vrb a 0.1u vrts vrt a YTD427 ytd426b test3 fthn 10k rstn reset testout0 ? 15 tmode0 ? 4 testin0 ? 11,13,15,16,17 testn18 testudr v v 1u clkout qinfo1c loop2a clk256k tsmpsel multi reset iosel bchif maslv clk1536 tamirp tamirm tamitp tamitm 10k x5 reset 15.36mhz ttl interface s/t reference point testin22,23 rbhw nc 10k 10k x2 10k 10k x16 10k 10k 10k 10k 10k 10k exid clk192k clk400 trpsel 10k 10k tsmpaut dd ss extclk rsync,tsync lpa,lp4b1,lp4b2 bchset0,1,2 uamitpn uamitm uamitmn uamitp testin12,14 tbhw powmon testin19,20,21,24 2sj278 2sj278 2sk2315 2sk2315 8(1%) 8(1%) u reference point 0.01u(10%) tdk vrya15 1u/160v kp4n12 15(1/2w) 15(1/2w) kp15n14 kp15n14 line activation circuit 4 7 8 6 5 3 2 1 nl322522t-3r3j (3.3uh) rxu sgr tdk trtepc9.8-0319c a 0.33u(10%) 3.9k(1%) 1.2k(1%) (3.3uh) 0.1u av dd dv dd dv ss av dd av ss x4 x4 x4 x4 figure a.1: pin connection example 21

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